1. Field of Invention
The present invention relates to voltage regulator circuits, and more particularly to low dropout regulators with wide input voltage range.
2. Related Art
Voltage regulators with a low dropout (LDO) are commonly used in the power management systems of computers, mobile phones, automobiles and many other electronic products. Power management systems use LDO regulators as local power supplies, where a clean output and a fast transient response are required. LDO regulators enable power management systems to efficiently supply additional voltage levels that are smaller than the main supply voltage. For example, the 5V or 12V power systems use LDO regulators to supply local chipsets and memories with a clean 2.5V and 3.3V signal.
Although LDO regulators do not convert power very efficiently, they are inexpensive, small, and generate very little frequency interference. Furthermore, LDO regulators provide a local circuit with a clean voltage that is unaffected by current fluctuations from other areas of the power system. LDO regulators are widely used to supply power to local circuits when the power consumption of the local circuit is negligible with respect to the overall load of a power system.
An ideal LDO regulator should provide a precise DC output, while responding quickly to load changes and input transients. Since LDO regulators are widely used in mass-produced products such as computers and mobile phones, simple design and low production costs of LDO regulators are also desirable.
A typical regulator consists of a feedback-control loop coupled to a pass element. The feedback-control loop modulates the gate voltage of the pass element to control its impedance. Depending on the gate voltage, the pass element supplies different levels of current to an output section of the power supply. The gate voltage is modulated such that the regulator outputs a steady DC voltage, regardless of load conditions and input transients. FIG. 1 shows a conventional circuit of a source-follow regulator. The source-follow regulator includes an N-type pass transistor 10, a feedback-control circuit 11, and a voltage divider 12 having a voltage divider point FB, and two resistors 121 and 122. The source-follow regulator receives an unregulated DC input voltage VIN and outputs a regulated DC output voltage VO. The feedback-control circuit 11 includes an error amplifier 15 and a reference voltage VREF is transmitted to the positive input of the error amplifier 15. The output of the error amplifier 15 is connected to the gate terminal G of the N-type pass transistor 10. The unregulated DC input voltage VIN is transmitted to the drain terminal D of the N-type pass transistor 10. The source terminal S of the N-type pass transistor 10 outputs the regulated DC output voltage VO. The DC output voltage VO is transmitted from the feedback-control circuit 11 through the voltage divider 12. The resistors 121 and 122 are connected in series between the regulated DC output voltage VO and the ground reference. The voltage divider point FB is between the resistors 121 and 122 and connected back to the negative input of the error amplifier 15.
The advantage of the source-follow regulator is good stability. The N-type pass transistor 10 provides attenuation to the feedback loop. The error amplifier 15 mainly controls the loop gain, which easily achieves adequate phase margin and gain margin. Another advantage of the source follow regulator is high PSRR (power supply rejection ratio). The N-type pass transistor 10 receives the unregulated DC input voltage VIN from the drain terminal D, which develops high impedance to resist the noise from the input voltage VIN to the output voltage VO. However, the problem of source follow regulator is high dropout voltage. The gate-to-source voltage Vgs1 has to be higher than a threshold voltage VT of the N-type pass transistor 10 in order to turn on the N-type pass transistor 10. Unfortunately, the difference in voltage between the unregulated DC input voltage VIN and the threshold voltage VT limits the highest output voltage VO. The drain-to-source voltage VDS1 is the voltage drop between the drain terminal D and the source terminal S of the N-type pass transistor 10 when the N-type pass transistor 10 is off-sate.
FIG. 2 shows a basic configuration of the LDO regulator. The LDO regulator includes a P-type pass transistor 20, a feedback-control circuit 21 and a voltage divider 22. The voltage divider 22 includes two resistors 221 and 222. The feedback-control circuit 21 includes an error amplifier 211 and the reference voltage VREF is transmitted to the negative input of the error amplifier 211. The output of the error amplifier 211 is connected to the gate terminal G of the P-type pass transistor 20.
The unregulated DC input voltage VIN is transmitted to the source terminal S of the P-type pass transistor 20. The P-type pass transistor 20 outputs the regulated DC output voltage VO from the drain terminal D. The DC output voltage VO is transmitted from the positive input of the error amplifier 211 through the resistors 221 and 222. The reference voltage VREF is transmitted to the negative input of the error amplifier 211. The advantage of the LDO circuits is low dropout voltage. The P-type pass transistor 20 is turned on as long as the source-to-gate voltage Vgs2 is higher than its threshold voltage. The output of the error amplifier 211 is pulled to ground, which achieves very low input-to-output voltage of LDO regulator. The drain-to-source voltage VDS2 is the voltage drop between the drain terminal D and the source terminal S of the P-type pass transistor 20 when the P-type pass transistor 20 is off-sate.
The problem of LDO regulator is that they are prone to instability at high input voltage VIN. The P-type pass transistor 20 contributes a significant gain into the feedback loop. Furthermore, due to the Miller effect, a parasitic capacitor 23 causes a high capacitance at the output of the error amplifier 211, which introduces a pole into the feedback loop to influence the transfer function of LDO regulator. The error amplifier 211 is thus required to have low output impedance to shift the pole to higher frequency for the loop stability. However, it is difficult to achieve low output impedance for the error amplifier 211, especially at high input voltage VIN.
Another problem of the LDO regulator is poor PSRR. The input voltage VIN is transmitted to the source terminal S of the P-type pass transistor 20, which is low impedance. The noise of the input voltage VIN disrupts the source-to-gate voltage Vgs2 of the P-type pass transistor 20 easily. Therefore, a need exists for an improved low dropout regulator that is with high PSRR and operates in wider range of input voltage.